The present invention relates generally to radio communication systems, and more particularly, to a flexible and efficient channelizer and de-channelizer architecture for use in a radio communication system.
The cellular industry has made phenomenal strides in commercial operations both in the United States and the rest of the world. Growth in major metropolitan areas has far exceeded expectations and is rapidly outstripping system capacity. If this trend continues, the effects of this industry""s growth will soon reach even the smallest markets. Innovative solutions are required to meet these increasing capacity needs as well as to maintain high quality service and avoid rising prices.
In addition to the challenges posed by a need for greater system capacity, the designers of future mobile communication systems and base stations have their own unique set of challenges. For example, a well known challenge in the industry is the desirability to provide a cost-effective and dynamically flexible system. System designers are interested in providing a system that is capable of dynamically handling the co-existence of a variety of different standards (e.g., Frequency Division Multiple Access, Time Division Multiple Access, etc.), dynamically allocating a number of channels for each individual standard and simultaneously handling multiple bandwidths without substantially increasing the hardware for the system. This need for dynamic flexibility is important to many base station operations, from downloading an individual configuration file for a base station during startup to the ability to reconfigure a site to handle continuously changing conditions (e.g., changing standards) on a frame-by-frame or even slot-by-slot basis.
FIG. 1 illustrates the dynamic allocation of a plurality of different standards over time on a frame-by-frame or slot-by-slot basis. As illustrated, all three slots of the first exemplary frame (i.e., Frame #1) are allocated to Digital American Mobile Phone System (DAMPS) transmissions which require only a small amount of bandwidth. The entire second exemplary frame is dedicated to EDGE transmissions which, as illustrated, have a higher bandwidth requirement than the DAMPS transmissions. The time slots of the Nth exemplary frame are allocated to both EDGE and Global Systems for Mobile communication (GSM) transmissions while the N+1 exemplary frame is allocated to wideband Code Division Multiple Access (CDMA) transmissions. As evident from FIG. 1, future systems will need to be able to support a plurality of different standards having different bandwidth requirements.
FIG. 2 illustrates a conventional base station receiver architecture including a digital channelizer able to support a number of different standards (e.g., FDMA#1 . . . K, TDMA#1 . . . M, CDMA#1 . . . N), each having a different number of channels, CX#Y (where X is the standard and Y is the number of carriers). As illustrated, the conventional base station receiver architecture comprises an antenna 210 that receives a Radio Frequency (RF) signal and transfers the signal to a RF front end 220 where it is down-converted to an intermediate frequency (IF). The RF front end 220 consists of such components as Low Noise Amplifiers (LNAs), filters and mixers. The IF signal is then converted to a digital signal via an Analog-to-Digital Converter (ADC) 230.
In order to achieve dynamic flexibility, the conventional base station may employ a digital channelizer 240 and channelizer algorithm. An exemplary channelizer/de-channelizer algorithm is the Modified Fast Convolution (MFC) algorithm which is described in detail in copending, commonly assigned, U.S. patent application Ser. No. 09/156,630, filed Sep. 18, 1998, and Swedish Patent No. 9802050-7 to Richard Hellberg, both of which are incorporated by reference herein. The function of a channelizer utilizing this algorithm is to filter out each channel sufficiently well so that signals at other frequencies do not interfere with the desired signal. The result is a band-limited signal that can be fed to a baseband processor (not shown) such as a rake detector for CDMA-based systems or an equalizer for TDMA-based systems.
The channelizer/de-channelizer algorithm described in U.S. patent application Ser. No. 09/156,630 is suitable for such channelization tasks as dynamically allocating parameters (e.g., filter parameters and data rates of different standards) and handling a varying number of channels and different standards having varying bandwidth requirements. While the channelizer/de-channelizer algorithm is both flexible and versatile, there is a need for a suitable hardware implementation for this algorithm that retains the algorithm""s flexibility and versatility, while at the same time does not introduce high computational costs or lead to a substantial increase in hardware.
FIG. 3 illustrates a typical hardware architecture for a digital channelizer. As illustrated, the digital channelizer comprises a number of different processing chains 400-1 to 400-N, each dedicated to one of a plurality of channels 1-N (N is generally a small number, such as 4). Each processing chain comprises a Numerically-Controlled Oscillator (NCO) and a group of cascaded digital filters. In operation, data from the ADC 230 for a first channel (e.g., Channel 1) is fed into the processing chain of the digital channelizer that is associated with the first channel, namely processing chain 400-1. NCO 410-1 down-converts the received frequency to a baseband frequency and generates I and Q components of the signal. The I and Q components are then fed into a data stream oriented set of cascaded digital filters. The cascaded filters are generally of different types, typically Cascaded Integrator-Comb (CIC), halfband or Finite Impulse Response (FIR) filters. The different filters have programmable parameters as filter coefficients, gain and decimation factors. The I and Q results are fed from the Nth filter of the first chain 400-1 to a baseband processor (not shown). One skilled in the art will appreciate that the other processing chains operate in a similar manner.
A digital channelizer or de-channelizer that is based on data stream processing on a per channel basis, such as the one illustrated in FIG. 3, will have limited flexibility within each individual channel. The computing resources for each channel is determined by the sum of all the different standard requirements for each individual module in the chain. Each individual module in the chain has to be specified for the standard that for that specific module have the toughest requirements. This means that the whole chain has to be over-specified to support all possible standards, resulting in overhead in silicon area and higher power dissipation. Additionally, since the number of channels is fixed (i.e., fixed to the number of processing chains supported by the channelizer), the system becomes inefficient in those situations where the number of channels needed is different from the fixed number supported by the digital channelizer.
There exists a need for a digital channelizer/de-channelizer that is able to dynamically adjust to continuously changing conditions without a substantial increase in computational cost or hardware.
The present invention provides a digital channelizer/de-channelizer architecture that, with a minimum amount of hardware, is capable of dynamically adapting to changing system requirements. According to exemplary embodiments of the present invention, the digital channelizer/de-channelizer, which is applied with a modified fast convolution algorithm, includes a plurality of dedicated, optimized, pipeline modules that may be dynamically adjusted for handling different bandwidths, a flexible number of channels, simultaneous multiple standards and a dynamic allocation of channels and standards.